Electronic Devices and Circuits, Circuit Analysis, Micro Processors and Micro Controllers,
VLSI Design, Computer Organization and Architecture, Switching Theory and Logic Design,
Digital Communications, Embedded Systems.
Parvathi, K.Satya Prasad, N.Vasantha, “Testing of Embedded SRAMs using Parasitic Extraction Method”, Robotic, Vision, Signal Processing and Power Applications (ROVISP), Empowering Research and Innovation, Editors: Ibrahim, H., Iqbal, S., Teoh, S.S., Mustaffa, M.T. (Eds.). ISBN 978-981-10-1721-6, Springer LNEE
Parvathi, N.Vasantha, K.Satya Prasad, “New Fault Model Analysis for Embedded SRAM Cell for Deep Submicron Technologies using Parasitic Extraction Method”, 2015 IEEE conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA) organized by Amritha Vishwa Vidyapeetham (University), School of Engineering, Bengaluru Campus, ISBN: 978-1-4799-7925-7, IEEE Xplore.
Ramakrishna Reddy, A, Parvathi, M. “Efficient carry select adder using 0.12µm technology for low power applications”, International Conference on Advances in Computing, Communications and Informatics (ICACCI), 2013 Digital Object Identifier: 10.1109/ICACCI.2013.6637231,Publication Year: 2013, Page(s): 550 – 553, IEEE Conference Publications ISBN: 978-1-4799-2432-5., ICACCI 2013 has been indexed in Scopus (Source record id: 21100278903), IEEE Xplore
Muddapu Parvathi, N.Vasantha, K.Satya Prasad, “Modified March C- With Concurrency in Testing, For Embedded Memory Applications”, International Journal of Electrical and Computer Engineering (IJECE), ISSN: 2088-8708, SCOPUS indexed Journal, IAES Publisher, Peer Reviewed and refereed with IF 3.02, DOI:http://dx.doi.org/10.11591/ijece.v2i5.1587
Parvathi, N.Vasantha, K.Satya Prasad, “Design of High Speed Low Power High Accurate (HS-LP-HA) Adder”, International Journal of Computer and Communication Engineering (IJCCE), ISSN:2010-3743, Vol:2, Issue 5, 2013, Pp:547-550, Peer Reviewed and refereed with IF 1
Parvathi, N.Vasantha, K.Satya Prasad, “Fault Model Analysis by Parasitic Extraction Method for Embedded SRAMs”, IJRET: International Journal of Research in Engineering and Technology Volume: 02 Issue: 12,PP:501-509, Dec-2013 eISSN: 2319-1163 | pISSN: 2321-7308, Peer Reviewed and refereed with IF 1.962.
Shilpa Darvesh, Parvathi, “1-Bit Nano CMOS Full-Adder cell for Energy-Efficient Arithmetic Applications”, International Journal of Electronics and Communication Engineering. ISSN 0974-2166 Volume 5, Number 3 (2012), pp. 181-187, Peer Reviewed and refereed with IF 3
Shilpa Darvesh, Parvathi,“1-Bit Full-Adder cell with Optimized Delay for Energy- Efficient Arithmetic Applications”, International Journal of Electronic Networks, Devices and Fields. ISSN 0974-2182 Volume 4, Number 1 (2012), pp. 1- 7, Peer Reviewed and refereed with IF 3
Uma Swarna, M Parvathi, “BCD Adder Design using new Reversible Logic for Low Power Applications”, Indian Journal of Science and Technology, Vol 10(30), PP:DOI: 10.17485/ijst/2017/v10i30/115514, August 2017, ISSN (Print) : 0974-6846, ISSN (Online) : 0974-5645
International Conference Proceedings:
Uma Swarna, M Parvathi, “BCD Adder Design using new Reversible Logic for Low Power Applications”, 3rd International Conference on Recent Developments in Science, Engineering and Technology (REDSET 2016), organized by School of Engineering, G.D. Goenka University, Gurgaon, India.
Parvathi, K.Satya Prasad, N.Vasantha, “Testing of Embedded SRAMs using Parasitic Extraction Method”, 9th International Conference on Robotics, Vision, Signal Processing & Power Applications (ROVISP 2016), Penang, Malaysia, organized by University Sains Malaysia.
Parvathi, N.Vasantha, K.Satya Prasad, “BIST Controller With Efficient Decoder and Adder for High Speed Embedded Memory Applications”, Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (IEEE Prime Asia 2012), ISBN: 978-1-4673-5065-5
Parvathi, N.Vasantha, K.Satya Prasad, “Design of High Speed Low Power High Accurate (HS-LP-HA) Adder”, 2012 International Conference on Electronic Computer Technology (ICECT 2012), 978-1-4673-1850-1/12
Nagaveni, M. Parvathi, “Designs, Implementation Methods and Comparisons for SRAM”, National Conference on Advanced Signal Processing, Embedded and Communication Systems (ASPECS-2016) 11th – 12th August 2016 Jointly organized by Dept. of ECE, CBIT and Research Centre Imarat, RDO Supported by TEQIP, In technical association with IETE Hyderabad Centre ISTE Chapter of CBIT.
N.Vasantha, M. Parvathi, “High speed BIST Controller for low power applications”, National Conference on Circuits Signals and Systems – 2015 (NCCSS 2015 January 22 – 24, 2015 ),
G.Mrudula, M.Parvathi, “A Palm Print Recognition System based on DM3730”, National Conference of Advanced Communication Trends ACT’12, pp: 173-176, 2012