ELECTRONICS AND COMMUNICATION ENGINEERING

Dr. M. Parvathi

Dr. M. Parvathi

Professor
parvathi.m@bvrithyderabad.edu.in

AICTE ID: 1-3541609603
JNTUH ID: 7286-170104-160426
Ratified Status: Ratified

Ph.D.: Testing of Embedded SRAM Using Modified March C- (MMC-) Algorithm and Parasitic Extraction Method, JNTUK, Kakinada, 2016
M.Tech.: Behavioural Description of 8255 PPI using Verilog, JNTUH, Hyderabad, 2002.  
B.Tech.: NITW (RECW), 1997

Teaching Experience: 21.5 Years
Research Experience: 8.10 Years
Industry Experience: Nil 

Scopus ID: 57220084017
WoS ID: AAU-9541-2020
Google Scholar ID: IiZNdG8AAAAJ
Vidwan ID: 104200
ORCID ID: 0000-0002-0564-3094

VLSI, Embedded Memory Testing, Digital Architectures, Low power designs, Machine Learning Applications

  1. Outstanding Research Award, by BVRITH, 2023
  2. Appreciation by IETE Society on session delivered a comprehensive knowledge sharing session (KSS) 78: Webinar – 110, on 16th of October, 2022 with topic “Embedded Memory Technology Trends and Test Challenges”.
  3. Appreciation award for Coordinating ATAL Online Faculty Development Programme, titled with “Machine Learning Applications in Micro-Nano VLSI Technologies” from 21/06/2021 to 25/06/2021.
  4. Best paper award in International Conference on Advances in Signal processing Communications and Computational Intelligence with Publication partner as American Institute of Physics (AIP) organized by Dept.ofECE, CMR Technical Campus, Hyderabad, on 23rd-24thJuly2021.
  5. IEEE Senior Member escalation award received on 15th Feb 2020
  6. Best Paper Award in IEEE International Conference On Computational and Characterization Techniques in Engineering & Sciences (CCTES-18) September 14-15, 2018, Organized by Department of ECE, EE & Physics, Integral University, Lucknow.
  7. Invited for Presentation of paper titled with “Two Cell Fault Models and Parasitic RC Test Method for Embedded SRAM” has been selected for presentation at 2ndInternational Conference on Information and Communication Technology 2018 (ICICTM’18), from Malaysian Institute of Information Technology during May 3rd -4th, 2018.
  1. Jahnavi, M., Madhavi, B., Ch. Varshini and Parvathi, M, “Design of sample-hold circuit for optimal operating conditions”, In Book: Recent Trends in VLSI and Semiconductor Packaging, Edited By T. Vasudeva Reddy, K. Madhava Rao, ISBN 9781041017868, Pp: 377-385, May 6, 2025 by CRC Press, DOI: 10.1201/9781003616399-45.
  2. Parvathi, M., Prasanna, T. A., and Chinnaiah, M. C. (2024). Design of an Exercise Monitoring System for Early Warning Heart Rate Risk Alarm with Confidence Intervals and Correlation Index Analysis. i-manager’s Journal on Embedded Systems, 13(1), 1-12. https://doi.org/10.26634/jes.13.1.21435
  3. Parvathi, “SRAM Memory Testing Methods and Analysis: An Approach for Traditional Test Algorithms to ML Models,” in book: Machine Learning Algorithms Using Scikit and TensorFlow Environments, IGI Global Publications, Nov-2023, Doi: 10.4018/978-1-6684-8531-6, ISBN: 9781668485316, pp: 243-258.https://opg.optica.org/ao/abstract.cfm?URI=ao-62-31-8366.
  4. Maddela, V., Sinha, S.K., Parvathi, M. et al.Comparative Analysis of Open and Short Defects in Embedded SRAM Using Parasitic Extraction Method for Deep Submicron Technology. Wireless PersCommun 132, 2123–2141 (2023). https://doi.org/10.1007/s11277-023-10704-w, SCI.
  5. Parvathi,“ActivityBasedAnalysisandPredictionStrategyfortheClassRoomPerformance Improvement”, Journal of Engineering Education Transformations, Volume34, January2021, Special issue, eISSN 2394-1707, Pp:686-693.
  6. Parvathi, Ch. Manaswini, “Prediction Analysis of Cancer Cells Using ML ClassificationAlgorithms”, Indian Journal of Public Health Research & Development, April-June 2021,Vol. 12,No. 2, ISSN: 0976-0245, Pp: 184-189.
  7. Parvathi, M. Ravikanth, and M.Neelakantappa, “Early Detection Support Mechanism inASDusingMLClassifier”,TurkishJournalofComputerandMathematicsEducation,Vol.12No.10 (2021), Pp: 4543-4549, Research Article, e-ISSN1309-4653.
  8. Parvathi, “Two Cell Fault Models and Parasitic RC Test Method for Embedded SRAM”,International Journal of Engineering & Technology (UAE), Vol. 7, No 4.29(2018), Pp: 235-238,DOI:10.14419/ijet.v7i4.29.26262.,ISSN:2227-524X.
  9. Parvathi, N.Vasantha, K.Satya Prasad, “BIST Architecture using Area Efficient LowCurrentLFSRforEmbeddedMemoryTestingApplications”,InternationalJournalofReconfigurable and Embedded Systems, Vol. 7, No. 1, March- 2018, pp.1~11, ISSN: 2089-4864,DOI: 0.11591/ijres.v7.i1.Pp1-11.
  10. Parvathi, “Designs, Implementation Methods and analysis for SRAM”, InternationalJournal of Current Engineering and Scientific Research, pISSN: 2393-8374, eISSN: 2394-0697,Vol-5,Issue-1-Part-III,Jan-2018, Peerreviewed,IF:3.241, Pp: 20-27.
  11. Swarna Uma, M Parvathi, “BCD Adder Design using new Reversible Logic for Low PowerApplications”,IndianJournalofScienceandTechnology,Vol10(30),DOI:10.17485/IJST/2017/v10i30/115514, August2017,ISSN (Print) :0974-6846,ISSN(Online) :0974-5645, Pp:1-7.
  12. Parvathi, N.Vasantha, K.Satya Prasad, “Fault Model Analysis by Parasitic ExtractionMethod for Embedded SRAMs”, IJRET: International Journal of Research in Engineeringand Technology Volume: 02 Issue: 12, Dec-2013 eISSN: 2319-1163 | pISSN: 2321-7308,PeerReviewed and refereed withIF 1.962, Pp:501-509.
  13. Parvathi,N.Vasantha,K.SatyaPrasad,“DesignofHighSpeedLowPowerHighAccurate(HS-LP-HA)Adder”,InternationalJournalofComputerandCommunicationEngineering (IJCCE), ISSN: 2010-3743, Vol: 2, Issue 5, September-2013, Peer Reviewedandrefereed withIF 1, Pp:547-550.
  14. MuddapuParvathi,N.Vasantha,K.SatyaPrasad,“ModifiedMarchC-withConcurrencyin Testing, For Embedded Memory Applications”, International Journal of Electrical andComputerEngineering(IJECE),Vol.2,No.5,October2012,ISSN:2088-8708,IAESPublisher,PeerReviewedandrefereedwithIF3.02,DOI:http://dx.doi.org/10.11591/ijece.v2i5.1587,Pp. 571-576. (UGC)
  15. ShilpaDarvesh,Parvathi,“1-BitNanoCMOSFull-AddercellforEnergy-EfficientArithmeticApplications”,InternationalJournalofElectronicsandCommunicationEngineering (IJECE) ISSN 0974-2166 Volume 5, Number 3 (2012), Peer Reviewed andrefereedwithIF3, Pp. 181-187.
  16. ShilpaDarvesh, Parvathi,“1-Bit Full-Adder cell with Optimized Delay forEnergy-Efficient Arithmetic Applications”, International Journal of ElectronicNetworks, Devicesand Fields (IJENDF) ISSN 0974-2182 Volume 4, Number 1 (2012), ,Peer Reviewed andrefereedwithIF3, Pp. 1-7.

25 International

  1. Parvathi, M., Pranathi, V., Varma, M., Satyanarayana, B.V.V. (2025). Voice-Based Smart System for Emotion Recognition and Regulation. In: Pareek, P., Mishra, S., Reis, M.J.C.S., Gupta, N. (eds) Cognitive Computing and Cyber Physical Systems. IC4S 2024. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, vol 599. Springer, Cham. https://doi.org/10.1007/978-3-031-77081-4_37
  2. Chinnaiah M.C., Narambhatlu J., Krishna H., Raju P.S., Parvathi M., Yamini B., Bhavani A.D., VardhanA.V. Light Intensity Analysis and Prediction for Dharana Using LabView 2024 IEEE International Conference on Information Technology, Electronics and Intelligent Communication Systems, ICITEICS 2024, Cited 0 times. DOI: 10.1109/ICITEICS61368.2024.10625566.
  3. Parvathi M., Praveenya T., Akshaya B., Leena V., BhuvaneshwariK.S., “Automated Shower for Physically Challenged Individuals (2024) Proceedings – 2024 4th International Conference on Pervasive Computing and Social Networking, ICPCSN 2024, pp. 907 – 913, Cited 0 times.DOI: 10.1109/ICPCSN62568.2024.00153.
  4. Parvathi, “Comparison of Prediction strategy for high accuracy in Autism Diagnostic System (ADS) using ML Classifiers”, International Conference on Advances in Signal Processing Communications and Computational Intelligence, AIP Conf. Proc. 2477, 030057-1–030057-8; https://doi.org/10.1063/5.0125291, Published by AIP Publishing. 978-0-7354-4523-9/$30.00, Pp: 030057-1to 030057-9, 2023
  5. M.Parvathi, V. Yashashwini, C.Yamini, A. GopiChandana, G.Pravalika, “Development of Novel Device for Women Safety”, International Conference on Advances in Signal Processing Communications and Computational Intelligence, AIP Conf. Proc. 2477, 030050-1–030050-7; https://doi.org/10.1063/5.0125288, Published by AIP Publishing. 978-0-7354-4523-9/$30.00, Pp: 030050-1 to 030050-8, 2023
  6. Keerthi T., Kumari A., Chinnaiah M.C., Parvathi M., Reddy C.D., Sumana D., “An Efficient Image Analysis Approach to Evaluate the Quality of Cotton Seeds (2023) 2023 4th International Conference for Emerging Technology, INCET 2023, Cited 0 times. DOI: 10.1109/INCET57972.2023.10170358.
  7. Parvathi and T. Amy Prasanna, “Performance Evaluation Metrics of NBA, NAAC, NIRF, and Analysis for Grade up Strategy”, Springer Nature Singapore Pte Ltd. 2023 M. Saraswat et al. (eds.), Proceedings of International Conference on Data Science and Applications, Lecture Notes in Networks and Systems 551, https://doi.org/10.1007/978-981-19-6631-6_8.
  8. Parvathi and M. C. Chinnaaiah, “Implementation and Performance Evaluation of Hybrid SRAM Architectures Using 6T and 7T for Low-Power Applications”, Springer Nature Singapore Pte Ltd. 2023, V. Bhateja et al. (eds.), Communication, Software and Networks, Lecture Notes in Networks and Systems 493, https://doi.org/10.1007/978-981-19-4990-6_22
  9. Parvathi M, “Architectural Designs and Performance Analysis of Adiabatic-based 6T, 9T, and 12T SRAM Cells”, Proceedings of the International Conference on Automation, Computing and Renewable Systems (ICACRS 2022) IEEE Xplore Part Number: CFP22CB5-ART: ISBN: 978-1-6654-6084-2
  10. Parvathi M, “Machine Learning based Interconnect Parasitic R,C, and Power Estimation Analysis for Adder Family Circuits”, Proceedings of the Sixth International Conference on I-SMAC (IoT in Social, Mobile, Analytics and Cloud) (I-SMAC-2022). IEEE Xplore Part Number: CFP22OSV-ART; ISBN: 978-1-6654-6941-8
  11. Maddela, S. K. Sinha, M. Parvathi and V. Sharma, “Fault Detection and Analysis in embedded SRAM for sub nanometer technology,” 2022 International Conference on Applied Artificial Intelligence and Computing (ICAAIC), Salem, India, 2022, pp. 1784-1788, doi: 10.1109/ICAAIC53929.2022.9793265.
  12. Parvathi, M., Pattan, A.B. (2022). ML-Based Comparative Analysis of Interconnect RCEstimation in Progressive Stacked Circuits. In: Suma, V., Fernando, X., Du, KL. Wang, H.(eds) Evolutionary Computing and Mobile Sustainable Networks. Lecture Notes on DataEngineeringandCommunicationsTechnologies,vol116.Springer,Singapore.https://doi.org/10.1007/978-981-16-9605-3_73
  13. VenkateshamMaddela, Dr.Sanjeet K Sinha and Parvathi Muddapu, “Extraction ofundetectableFaultsin6T-SRAMCell”,InproceedingsofInternationalConferenceonCommunication,ControlandInformationSciences(ICCISc-2021),OrganizedbyGovernmentEngineeringCollege,IdukkiPainavu,Kerala,incollaborationwithIEEE-KeralaSection, 2021, ISBN:978-1-6654-3128-6, Pp: 13-17.
  14. Maddela, V, Sinha, S.K., Muddapu, Parvathi., “Analysis of Open Defect Faults in Single 6T SRAM Cell Using R and C Parasitic Extraction Method”, Proceedings of IEEE International Conference on Disruptive Technologies for Multi-Disciplinary Research and Applications, CENTCON 2021, ISBN:978-1-6654-0018-3, pp. 213–217, Feb 2022.
  15. VenkateshamMaddela, Dr.Sanjeet K Sinha and Parvathi Muddapu, “Study on Paradigm of Variable Length SRAM Embedded Memory Testing”, Proceedings of the Fifth International Conference on Electronics, Communication and Aerospace Technology (ICECA 2021), ISBN: 978-1-6654-3523-9, 978-1-6654-3524-6/21/$31.00 ©2021 IEEE, Pp:129-133.
  16. VenkateshamMaddela, Dr.Sanjeet K Sinha and Parvathi Muddapu, “Open DefectFault Analysis in Single Cell SRAM Using R, and C Parasitic Extraction”, InternationalConference on Information & Communication Engineering(ICICE-2021), February 11 – 13,2021,ISBN: 978-93-5437-185-1, Pp:30-31.
  17. Parvathi M, Ravikanth M and Neelakantappa M, “Early Detection Support Mechanism in Autism Spectrum Disorder using ML Classifier”, Proceedings Of International Conference On Information & Communication Engineering, ISBN: 978-93-5437-185-1, 2021, Pp: 34-35.
  18. Muddapu, “Camera and Biometric based Vehicle Monitoring System for Public Safety (2020) Proceedings of 2020 IEEE-HYDCON International Conference on Engineering in the 4th Industrial Revolution, HYDCON 2020, art. no. 9242840, Cited 5 times. DOI: 10.1109/HYDCON48903.2020.9242840.
  19. Parvathi M. (2020), “High-Accurate, Area-Efficient Approximate Multiplier for Error- Tolerant Applications”, In: Pant M., Kumar Sharma T., Arya R., Sahana B., Zolfagharinia H. (eds) Soft Computing: Theories and Applications. Advances in Intelligent Systems and Computing (SOCTA2020), vol:1154, Springer, https://doi.org/10.1007/978-981- 15-4032-5_10.
  20. Parvathi, B. Himasree, T. Bhavyasree, “Novel Test Methods for NPSF Faults in SRAM”, Proceedings inIEEE International ConferenceOn Computational and Characterization Techniques in Engineering & Sciences (CCTES-18) September 14-15, 2018, Organized by Department of ECE, EE & Physics, INTEGRAL UNIVERSITY, LUCKNOW, P-35. DOI: 10.1109/CCTES.2018.8674087.
  21. Parvathi, K.Satya Prasad, N.Vasantha, “Testing of Embedded SRAMs using Parasitic Extraction Method”, Proceedings in Robotic, Vision, Signal Processing and Power Applications (ROVISP-2017), Empowering Research and Innovation, Editors: Ibrahim, H., Iqbal, S., Teoh, S.S., Mustaffa, M.T. (Eds.), ISBN 978-981-10-1721-6, Jan-2017, Springer LNEE, Pp:47-61.
  22. Parvathi, “New March Elements for Faults due to Open Defects in eSRAM” Proceedings in First International Conference on Digital Contents and Applications (DCA 2018), Sydney, Australia, January 10 – 12, 2018, ISBN 978-81-933584-3-6, Vol:1,P-06.
  23. Parvathi, N.Vasantha, K.Satya Prasad, “New Fault Model Analysis for Embedded SRAM Cell for Deep Submicron Technologies using Parasitic Extraction Method”, Proceedings in 2015 IEEE conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA) organized by AmrithaVishwa Vidyapeetham (University), School of Engineering, Bengaluru Campus, ISBN: 978-1-4799-7925-7, 9781479979271, Pp:1-6. IEEE Publications, DOI: 10.1109/VLSI-SATA.2015.7050471.
  24. Ramakrishna Reddy, A, Parvathi, M. “Efficient carry select adder using 0.12µm technology for low power applications”, Proceedings in International Conference on Advances in Computing, Communications and Informatics (ICACCI), 2013 DOI: 10.1109/ICACCI.2013.6637231,Publication Year: 2013, IEEE Conference Publications ISBN: 978-1-4799-2432-5, Pp: 550 – 553.
  25. Parvathi, N.Vasantha, K.Satya Prasad, “BIST Controller With Efficient Decoder and Adder for High Speed Embedded Memory Applications”, Proceedings in Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (IEEE Prime Asia-2012),ISBN:978-1-4673-5065-5,Pp:234-239,DOI:10.1109/PrimeAsia.2012.6458661

3 (National)

  1. Parvathi, “Designs, Implementation Methods and Comparisons for SRAM”, Proceedings in National Conference on Advanced Signal Processing, Embedded and Communication Systems (ASPECS- 2016) 11th – 12th August 2016 Jointly organized by Dept. of ECE, CBIT and Research Centre Imarat, DRDO Supported by TEQIP, in technical association with IETE Hyderabad Centre ISTE Chapter of CBIT
  2. Vasantha, M. Parvathi, “High speed BIST Controller for low power applications”, Proceedings in National Conference on Circuits Signals and Systems – 2015 (NCCSS 2015 January 22 – 24, 2015 ),
  3. G.Mrudula, M.Parvathi, “A Palm Print Recognition System based on DM3730”, Proceedings in National Conference      of Advanced Communication Trends ACT’12, 2012, pp: 173-176.
  1. “AI Enabled Framework for Early Diagnosis Of Autism Spectrum Disorder (ASD)” – ThePatentOfficeJournalNo.11/2021Dated12/03/2021,ApplicationNo.202141008949A,PublicationDate: 12/03/2021, Pp: 12850-12851.
  2. “AnAIEnabledMethodforParasiticR&CEstimationinProgressiveStackedSRAMCircuits” – The Patent Office Journal No. 17/2021 Dated 23/04/2021, ApplicationNo.202141016526A, Publication Date: 23/04/2021.
  3. “Carbon nano tube field effect transistor based memory device”, ThePatentOfficeJournalNo.24/2023Dated16/06/2023,ApplicationNo.202341020130A,PublicationDate: 16/06/2023, Pp: 12850-12851.
  4. “Design of Sentry Robot for Surveillance and Security”, Design application number 6272417 Filing date (provisional) 31 March 2023.
  • AICTEATAL Online Faculty Development Programme, titled with “Machine Learning Applications in Micro-Nano VLSI Technologies” from 21
  • IEEE: Senior Member No: 90763176
  • IETE: Life Member M-218887
  • ISTE: Life Member LM64189
  • Invited by IETE Society, delivered session during comprehensive knowledge sharing session (KSS) 78: Webinar – 110, on 16th of October, 2022 with topic “Embedded Memory Technology Trends and Test Challenges”.

Nil

  1. Reviewer IEEE Transactions on Circuits and Systems II: Express Briefs
  2. Reviewer and Advisory / Technical Program Committee member for INSC (Institute of Scholars) Journals as well as conferences since Dec 6, 2019.
  3. Reviewer for Eighth International Conference In Transformations in Engineering Education (ICTIEE-2021)
  1. CoordinatedAICTEATALOnlineFacultyDevelopmentProgrammeon”MachineLearningApplicationsin Micro-Nano VLSI Technologies” from 21/06/2021to 25/06/2021
  2. Proceeding Committee member for “International Conference on “Microelectronics, Electromagnetic and Telecommunications”,(ICMEET2017),at BVRITH, ISSN 1876-1100 ISSN 1876-1119 (electronic) Lecture Notes in Electrical Engineering ISBN 978-981-10-7328-1ISBN 978-981-10-7329-8 (eBook).
  3. Two day workshop on “IC Design Flow Using Microwind” on 6-7th& 14-15th March2017in the Dept. of ECE for IV ECE, 2017.

Events Organized:

  1. “Innovate Circuit League (ICL)”, a competition to build circuit using online simulator, organized on 2nd, April, 2025, as part of Synergia-2025, National level Tech Fest, BVRITH.
  2. “Thandav”, a dance competition, organized on 3rd, April, 2025, as part of Synergia-2025, National level Tech Fest, BVRITH.
  3. “TRONICS TRIVIA”, (Rounds of Quiz competition)is organized during Medhanvesh-2024 Technical fest on : 22-03-2024, BVRITH
  4. “Technomorphic INDAI by 2047”, organized during Engineers Day Celebrations-2023, happened on 15th September 2023
  5. “Sumo Robota (Robots talent competition)” is organized during Medhanvesh-2023 Technical fest on 25-02-2023.
  6. Under IEEE SB Udbhava organized Session on “Advance Info @IEEE Explore”, on 4th
  7. CoordinatedAICTEATALOnlineFacultyDevelopmentProgrammeon”MachineLearningApplicationsin Micro-Nano VLSI Technologies” from 21/06/2021to 25/06/2021.
  8. “IEEE Membership Drive” by Mr.G Rajesh, SN Mentor, IEEE Hyd-Section, on 8th August,2020.
  9. National Level Techno Quiz contest, on Aptitude, Reasoning, Python, Current Affairs, on17th&18th July2020 under IEEESB, BVRITH.
  10. IEEE Annual Day on 6th March 2020, with a technical talk on “Interesting Facts on Technology” by Mr.M.Dinakar, Staff Engr, Xilinx.
  11. IEEEXPLORE session by, Mr.MSSrinivasa,IEEEManagerSouth,on17THJuly,2019
  12. TechnicalTalkon“TheRoleofGISInDisasterManagementInThePresentDayScenario‟, by Dr. V. Bhanu Murthy, Outstanding scientist/Associate Director NRSC, on24THJuly, 2019 under IEEESB-CIS/GRSS Student Chapter.
  13. IEEE Membership Drive- by Dr. K. Vijaya Latha from GRIET, on 6th September, 2019,under IEEESB, BVRITH.
  14. ‘Success Stories and Space Concepts of ISRO’, event on behalf of Space week on 1stOctober,2019, under IEEE SBUdbhava.

Workshops Organized:

  1. Two-day workshop on “Research and Ethics”,by Dr. Abdul Solman Moiz, Professor at UOH, organized on behalf of R&D, BVRITH in collaboration with IEEE Hyderabad Section &GRSS, on 28th&29th
  2. Two day workshop on “IC Design Flow Using Microwind” on 6-7th& 14-15th March2017in the Dept. of ECE for IV ECE, 2017.
  3. Organized VLSI workshop for 3 days on “Current trendsin VLSI design using FPGA/CPLD and SoC”in M.R.I.T.S, 2012

 

Seminars/Webinars Organized:

  1. On behalf of R&D cell, conducted webinar on “Machine Learning Augmented Device Modelling” Speaker & Guest: Dr.AvirupDasgupta, Assistant Professor, IITRoorkee, Founder-FIC-DiRAC Lab, on Feb 20, 2025
  2. Being R&D Coordinator, organized technical knowledge sharing sessions in Collaboration with IEEESB UDBHAVA, on “Diabetic Prediction using ML”, on 1stOctober 2021.
  3. Guest lecture organized in the dept on “Remote sensing and Signal processing” by Dr.G.Prasad, Scientist ‘G’, NRSC October2017.
  4. Technical Seminar on “QUICS Learn and Practice” on 04-07-2015, by Dr. L. Satya Prasad, Principal, SCETW.
  5. Technical Seminar on “Biomedical Signal Processing” on 04-08-2015, by Dr.P.V. Gopi Krishna Rao, Professor & Head, Research and Development, RGMCET, Kurnool.
  6. “Challenges in the current technology” by Mr.Srikanth Goudey, System Architect, AMD, 2012.
  7. “Satellite and its Components–EmbeddedDesign”byMr.Tagore,Sr.Engr,TATAGroup.2011
  8. “OpenSourceHardware”byMr.SriPPrashanth,ASICDesignConsultantatAMD.2011
  9. Screening on “Earth Climate” by IYCN(Indian Youth climate Network) along with US Consulate General, Hyderabad, 2010
  10. M.G.P.L.Narayan, thethen IEEEHyd chair.2010
  1. Conferences attended, presented: 25
  2. FDPs attended: 52
  3. Workshops Attended: 45
  • Department R&D Incharge
  • M.Tech Coordinator