ELECTRONICS AND COMMUNICATION ENGINEERING

Dr. Y. Alekhya

Dr. Y. Alekhya

Assistant Professor
alekhya.yalla@bvrithyderabad.edu.in

AICTE ID: 1-9593721506
JNTUH ID: 2040-250301-101305
Ratified Status: –

Ph.D.: Design and Investigation of High Performance Energy Efficient SRAM Cell with Improved Stability, VIT-AP, 2023
M.Tech.: Design and Development of FPGA based Automation System, MVGR College of Engineering, JNTUK,2012
B.Tech.: MVGR College of Engineering, JNTUK, 2009

Teaching Experience: 11.8 Years
Research Experience: Nil
Industry Experience: Nil

Scopus ID: 57210555969
WoS ID: –
Google Scholar ID: k0BVzyUAAAAJ
Vidwan ID: 606735
ORCID ID: 0000-0002-9816-3064

VLSI, Low Power Memory Circuits, Digital CMOS VLSI Design

  1. Secured First Prize in technical paper at EJIVE-2008 on “DIGITAL IMAGE PROCESSING AND IMAGE EDITING” held by Pragathi EngineeringCollege, Kakinada.
  2. Secured Best Paper Award in event ACCT (Advanced Communication and Computer Technologies)-2012 on “FPGA BASED SMART TESTING TOOL” held by IETE at NSTL Visakhapatnam.
  3. Topper in M. Tech ECE Department(2010-2012).
  4. Performed Very Good in Hackathon conducted from 15th Feb- 1st Mar 2022 by IIT Hyderabad, sponsored by Synopsys in association with VLSI System Design (VSD) Pvt.
  1. Alekhya, Yalla. Nanda, U., (2019). Quasi FGMOS 6T SRAM Cell Design: A Strategy for Low Power Applications. International Journal of Nanoscience. (SCI, IF: 0.8) doi: 10.1142/S0219581X20400049.
  2. Alekhya, Yalla., Nanda, U. (2023).” CNTFET-based Data Independent Power Efficient and Robust 8T SRAM Cell”, ECS Journal of Solid-State Science and Technology. (SCI, IF: 2.070) doi:10.1149/2162-8777/acd7a1.
  3. Alekhya, Y., Nanda, U., (2022).” Investigation of CNTFET Based Energy Efficient Fast SRAM Cells for Edge AI Devices,” Silicon, 8815–8830. (SCI, IF: 2.941) doi:10.1007/s12633-021-01589-0.
  4. Alekhya, Y., and J. Sudhakar. “Design of 64-bit SRAM using lector technique for low leakage power with read and write enable.” IOSR Journal of VLSI and Signal Processing (IOSRJVSP) 7 (2017): 10-19.
  5. Dilip, Bhaskar, Y. Alekhya, and P. Divya Bharathi. “FPGA implementation of an advanced traffic light controller using Verilog HDL.” International Journal of Advanced Research in Computer Engineering & Technology (IJARCET) 1.7 (2012): 2278-1323.
  6. Alekhya, Y., and J. Sudhakar. “Design Analysis of SRAM Cell with Improved Noise Margin based on Aspect Ratio Adjustments.” HELIX 8.1 (2018): 2645-2650.
  7. Alekhya, G. Anjaneyulu. “Design and Development of FPGA based Automated Test System.” International Journal of Electronics & Communication Technology (IJECT) Vol .3, Issue 3, July-Sep 2012.
  8. B. Dilip, Y. Alekhya, U. Sandhya Rani “Low-Power and High-Speed CMOS Circuits using Leakage Reduction Techniques. “International Journal of Electronics & Communication Technology (IJECT) Vol .3, Issue 3, Oct-Dec 2012.
  1. Yalla, U. Nanda, C. K. Pandey and S. Ye, “Reversible High Speed Binary Content Addressable Memory array design using Transmission Gate Logic,” 2023 3rd International conference on Artificial Intelligence and Signal Processing (AISP), VIJAYAWADA, India, 2023, pp. 1-6, doi: 10.1109/AISP57993.2023.10134833.
  2. Alekhya, Yalla., Nanda, U., Quasi FGMOS Inverter: A Strategy for low power applications,” 2019 Devices for Integrated Circuit (DevIC), Kalyani, India, 2019, pp. 211-215, doi: 10.1109/DEVIC.2019.8783765.
  3. Alekhya, U. Nanda,” Strategical Survey on Static Random Access Memory: A Bibliometric Study,” 2022 2nd International Conference on Intelligent Technologies (CONIT), Hubli, India, 2022, pp. 1-15, doi: 10.1109/CONIT55038.2022.9847746.
  4. Alekhya, T.Sindhusha, S.S.Mahalakshmi, N.Swathi and S.V.Sharvani, “Design of SRAM based BTI Sensor for Improved Cell Stability,” SSRG International Journal of Electronics and Communication Engineering, vol. 5, no. 8, pp. 5-13, 2018. Crossref, doi.org/10.14445/23488549/IJECE-V5I8P102.
  5. Sudhakar, J., Alekhya, Y., Syamala, K.S. (2018). A Dual-Rail Delay-Insensitive IEEE-754 Single-Precision Null Convention Floating Point Multiplier for Low-Power Applications. In: Saini, H., Singh, R., Reddy, K. (eds) Innovations in Electronics and Communication Engineering. Lecture Notes in Networks and Systems, vol 7. Springer, Singapore. doi.org/10.1007/978-981-10-3812-9_13.

Nil

Nil

IEEE Member (98243663)

Nil

Nil

Scientific reports Journal

Nil

  1. Participated in “Workshop on system design using XILINX FPGA’s” conducted by the Department of ECE, GVP College of Engineering, Visakhapatnam and CoreEL Technologies,Bangalore.
  2. Participated in 2-day Workshop on “Mixed Signal IC Design using EDA Tools (WMSID- 16)”,
  3. Participated in “WORKSHOP ON DSP ACCOUSTYX” in Shaastra 2007 atIIT-Madras.
  4. Participated in 2-day Workshop on “Technical writing and presentation with latex” conducted by Vellore Institute of Technology, Vellore,2020.
  5. Participated in 5- Day Workshop on “VLSI Device and Circuit Design Tools (Online)” organized by the School of Electronics Engineering (SENSE), VIT-AP University, Amaravati (AP),2021.
  6. Participated in 5- Day Workshop on “Technical Report Writing using LaTeX” organized by the School of Electronics Engineering (SENSE), VIT-AP University, Amaravati (AP),2021.
  7. Participated in 5- Day Workshop on “Digital Synthesis Using Cadence Genus Tool”, organized by the School of Electronics Engineering (SENSE), VIT-AP University, Amaravati (AP),2021.
  8. Attended a “A Six Day Faculty Development Program on Virtual industry and simulation software (VISS-2016),
  9. Attended a Quality improvement program “Instructional Design and Delivery Systems” conducted by VIEW, Nov,2017.
  10. Attended a “A Five-Day Faculty Development Program on “SCILAB and NGSPICE” conducted by Universal College of Engineering and Technology, Guntur,2020.
  11. Participated in A Five-Day Faculty Development Program on “Artificial Intelligence in Revolutionizing Healthcare” conducted by NATIONAL INSTITUTE OF TECHNOLOGY PUDUCHERRY, KARAIKAL, 2021.
  12. Attended a Five-Day Faculty Development Program on “Machine Learning Techniques in VLSI Design” conducted by MS Ramaiah Institute of Technology, 2021.
  13. Attended a Five-Day Faculty Development Program on “IPR Awareness and Patent Prosecution” conducted by Oriental Institute of Science and Technology, Bhopal during 13th – 17th July 2021.
  14. Attended a One Week Faculty Development Program on “Trends and Challenges in Advanced VLSI System Design” conducted by Sagi Rama Krishnam Raju Engineering College (A), Bhimavaram during 21st to 26th February 2022.
  15. Attended a One Week online Faculty Development Program “Emerging Trends in Electronics and Communication for IoT Applications” conducted by IMS Engineering College, Ghaziabad, Uttar Pradesh, India during 4 July – 8 July, 2022
  • Counselling Co-ordinator
  • Dept. Library Co-ordinator